The subject of chip scale packaging has been the focus of intense study in the industry for many years. One very promising technology involves securing small, resilient members onto a suitable substrate and using these members to effect contact between an active device and other circuitry.
Commonly-owned U.S. patent application Ser. No. 08/152,812 filed 16 Nov. 93 (now U.S. Pat. No. 4,576,211, issued 19 Dec. 95), and its counterpart commonly-owned copending “divisional” U.S. patent application Ser. No. 08/457,479 filed 01 Jun. 95 (status: pending) and Ser. No. 08/570,230 filed 11 Dec. 95 (status: pending), all by KHANDROS, disclose methods for making resilient interconnection elements for microelectronics applications involving mounting an end of a flexible elongate core element (e.g., wire “stem” or “skeleton”) to a terminal on an electronic component, coating the flexible core element and adjacent surface of the terminal with a “shell” of one or more materials having a predetermined combination of thickness, yield strength and elastic modulus to ensure predetermined force-to-deflection characteristics of the resulting spring contacts. Exemplary materials for the core element include gold. Exemplary materials for the coating include nickel and its alloys. The resulting spring contact element is suitably used to effect pressure, or demountable, connections between two or more electronic components, including semiconductor devices.
Commonly-owned, copending U.S. patent application Ser. No. 08/340,144 filed 15 Nov. 94 and its corresponding PCT Patent Application No. PCT/US94/13373 filed 16 Nov. 94 (WO95/14314, published 26 May 95), both by KHANDROS and MATHIEU, disclose a number of applications for the aforementioned spring contact elements, such as making an interposer. The application also discloses techniques for fabricating contact pads (contact tip structures) at the ends of the spring contact elements.
Commonly-owned, copending U.S. patent application Ser. No. 08/452,255 filed 26 May 95 and its corresponding PCT Patent Application No. PCT/US95/14909 filed 13 Nov. 95 (WO96/17278, published 06 Jun. 96), both by ELDRIDGE, GRUBE, KHANDROS and MATHIEU, disclose additional techniques and metallurgies for fabricating spring contact elements such as composite interconnection elements, and for fabricating and mounting contact tip structures to the free ends (tips) of the composite interconnection elements.
Commonly-owned, copending U.S. patent application Ser. No. 08/558,332 filed 15 Nov. 95 by ELDRIDGE, GRUBE, KHANDROS and MATHIEU, and its corresponding PCT Patent Application No. US95/14885 filed 15 Nov. 95 by ELDRIDGE, GRUBE, KHANDROS and MATHIEU disclose methods of fabricating resilient contact structures which are particularly well-suited to fabricating spring contact elements directly on semiconductor devices.
The present invention addresses and is particularly well-suited to making interconnections to modern microelectronic devices at a fine-pitch. As used herein, the term “fine-pitch” refers to microelectronic devices that have their terminals (in the case of the present invention, their interconnection elements) disposed at a spacing of less than about 5 mils, such as 2.5 mils or 65 μm. The invention however is useful with devices with any pitch (e.g. millimeter or larger), but particularly pitch below about 15 mils (375 μm). As just one useful example, a device may be fitted with springs in an area array with spacing of approximately 10 mils (250 μm). A corresponding connection element would have the same pitch as the contact areas of the springs. For example, a corresponding socket would have a corresponding pattern of capture pads with the same pitch to receive the array of springs.
In the main are described, hereinafter, socketably receiving electronic components which are semiconductor devices, and which have interconnection elements which are elongate interconnection elements, more particularly which are spring contact elements extending from a surface thereof. As used herein, a semiconductor device having spring contact elements mounted thereto is termed a springed semiconductor device.
A springed semiconductor device may be interconnected to an interconnection substrate in one of two principal ways. It may be permanently connected such as by soldering the free ends of the spring contact elements to corresponding terminals on an interconnection substrate such as a printed circuit board. Alternatively, it may be reversibly connected to the terminals simply by urging the springed semiconductor device against the interconnection substrate so that a pressure connection is made between the terminals and contact portions of the spring contact elements. Such a reversible pressure connection can be described as self-socketing for the springed semiconductor device.
The ability to remove a springed semiconductor device from a pressure connection with an interconnection substrate would be useful in the context of replacing or upgrading the springed semiconductor device. A very useful object is achieved simply by making reversible connections to a springed semiconductor device. This is particularly useful for testing the springed semiconductor device. This also is useful for mounting, temporarily or permanently, to an interconnection substrate of a system to (1) burn-in the springed semiconductor device or (2) to ascertain whether the springed semiconductor device is measuring up to its specifications. As a general proposition, this can be accomplished by making pressure connections with the spring contact elements. Such contact may have relaxed constraints on contact force and the like. The present invention discloses a number of techniques for socketing to springed semiconductor devices.
Commonly-owned, copending U.S. patent application Ser. No. 08/533,385 filed 18 Oct. 95 by DOZIER, ELDRIDGE, GRUBE, KHANDROS and MATHIEU, and its corresponding PCT Patent Application No. US95/14842 filed 13 Nov. 95 by DOZIER, ELDRIDGE, GRUBE, KHANDROS and MATHIEU disclose socket substrates having spring contact elements for making reversible connections to an active semiconductor device. The socket is in turn secured and connected to electronic circuitry. In a most general manner, the present invention addresses what could be considered to be an analogous but reverse situation—namely, making reversible connections to electronic components having spring contact elements with socket substrates.
Commonly-owned, copending U.S. patent application Ser. No. 08/784,862 filed 15 Jan. 97 by KHANDROS AND PEDERSEN, and its counterpart PCT Patent Application No. US97/08604 filed 15 May 97 by KHANDROS AND PEDERSEN disclose a system for wafer-level burn-in and test wherein a plurality of relatively small, active electronic components, such as application-specific integrated circuits (ASICs) are mounted to a relatively large interconnection substrate. A plurality of semiconductor devices are resident on a wafer under test (WUT).
Spring contact elements extend from the surfaces of the semiconductor devices and are suitably, but are not limited to, free-standing, elongate, interconnect elements such as are disclosed in the aforementioned commonly-owned, copending U.S. patent application Ser. No. 08/452,255 filed 26 May 95 and its counterpart PCT Patent application number US95/14909 filed 13 Nov. 95. As illustrated in FIG. 3B therein, a plurality of indentations, suitably in the form of inverse pyramids extend into an ASIC from the faces thereof. Metallization is applied to the sidewalls of these indentations, establishing electrical communication with circuitry elements of the ASIC.
In use, as an ASIC and the WUT are brought together, the tips of the spring contact elements on the WUT enter the indentations in the ASIC and engage the sidewalls of the indentations with sufficient force to ensure a reliable electrical pressure connection. As illustrated in FIG. 3C therein, each ASIC alternatively has a plurality of pads (terminals) formed in a conventional manner on its front surface, and a layer of insulating material. Such a silicon die may be micromachined to have a plurality of apertures extending therethrough and aligned with the contact pads and may be disposed over the front surface of the ASIC. The layer of insulating material provides comparable “capture” capability as the indentations formed in the ASICs. FIGS. 5A–5C of these patent applications illustrate a technique for making conductive vias through an ASIC, wherein indentations (first and second hole portions) are created from both sides of the ASIC until they become contiguous with one another. Then, a conductive layer (e.g., tungsten, titanium-tungsten, etc.) is deposited, such as by sputtering into the first and second hole portions, resulting in a first conductive layer portion extending into the first hole portion and a second conductive layer portion extending into the second hole portion. This is particularly interesting when the first and second hole portions are on opposite sides of a silicon substrate such as a wafer. Then a mass of conductive material (e.g., gold, nickel, etc.) is applied to connect (bridge) the conductive layers in the two hole portions. This mass of conductive material is suitably applied by plating.
Commonly-owned, copending U.S. patent application Ser. No. 09/108,163, filed 30 Jun. 1998 by ELDRIDGE, GRUBE, KHANDROS, MATHIEU, PEDERSEN, and STADT discloses a number of techniques for making reversible connections to a springed semiconductor device for the purpose of burning-in the springed semiconductor device and ascertaining whether the springed semiconductor device is capable of performing up to its specifications. For example, FIG. 2 of the patent application illustrates a technique wherein the springed semiconductor device is urged against an interconnection substrate such as a printed circuit board (PCB) so that the tips of the spring contact elements come into pressure contact with a corresponding plurality of terminals on the PCB to establish a pressure connection therewith. For example, FIG. 4 of the patent application illustrates a technique wherein end portions of the spring contact elements are inserted into plated through-hole terminals of an interconnection substrate such as a printed circuit board. For example, FIG. 5A of the patent application illustrates a technique wherein the ends of the spring contact elements are brought into contact with corresponding ones of a plurality of concave terminals of an interconnection substrate. The concave terminals are formed like plated through-holes that have an upper portion in the form of a cone or pyramid which has its base at an upper surface of the interconnection substrate and its apex (point) within the interconnection substrate. FIG. 5B of the patent application illustrates concave terminals, each in the form of a hemisphere which has its base at an upper surface of the interconnection substrate and its apex within the interconnection substrate. FIG. 5C of the patent application illustrates concave terminals that have an upper portion in the form of a trapezoidal solid which has relatively wider base portion at an upper surface of the interconnection substrate and its relatively more narrow base portion within the interconnection substrate. In each of the examples of FIGS. 5A, 5B and 5C of the patent application, the tip of the spring contact structure enters the concave terminal at its widest portion, thus allowing easier entry and guiding or “capturing” the ends of the spring contact elements with the terminals.